Conversion of analog electrical signals to digital data is central to many electronic functions, for example to facilitate digital signal processing (DSP) of the digital data representing an input analog signal. In many cases, processing the signal in the digital domain provides greater accuracy, repeatability, and often lower system cost than analog processing.
Different types of analog to digital converters (ADC's) have been developed to efficiently convert a wide variety of analog signals. Some key attributes of an analog signal include frequency range, amplitude range, and desired signal to noise ratio. Different ADC's have been developed to address the wide differences in analog signals to be converted.
One class of ADC is known as a flash converter. Such a converter has typically 2^n comparators, each having a different threshold voltage applied to a first input, where the 2^n threshold voltages are substantially equally spread across a range from a lower reference voltage to a higher reference voltage. The input analog signal, which has a range substantially the same as the threshold voltage range, is coupled to the second input of all comparators. As the input analog voltage increases, progressively more comparators change state from low to high logic levels as the input analog voltage exceeds the threshold level of comparators. The resulting 2^n outputs of the comparators are sometimes referred to as thermometer code, due to the progressive nature of output change as input voltage rises. This thermometer code is then logically decoded to a binary representation of the input voltage. A primary advantage of the flash converter is its speed, since all comparators process the input concurrently, and the delay through the thermometer code to binary logic can be made quite small. The significant disadvantage of such a converter is the need for 2^n comparators. For example, a 4-bit conversion is accomplished with only 16 comparators, while a 9-bit conversion requires 512 comparators.
A class of ADC known as pipelined converter retains much of the speed advantage of the flash converter while dramatically reducing the number of comparators. In a pipelined ADC (PADC), the input analog signal is digitized in a first stage flash converter having a fraction of the desired total number of bits—for example, a 3-bit converter using eight comparators. The resulting 3-bit number is then a coarse estimate of the actual voltage. This 3-bit number is then input to a first stage multiplying digital to analog converter (MDAC), wherein it is accurately converted back to an analog voltage which is subtracted from the input analog signal. This difference voltage, which in the absence of error has one-eighth the peak to peak range of the input analog signal, is then multiplied by 2^n or, in this example, eight, yielding a residue voltage having substantially the same peak to peak range as the input analog signal. This amplified residue voltage is then coupled to the input of a second stage substantially identical to the first stage.
Because the residue voltage from the first stage has substantially the same dynamic range as the input to the first stage, the reference voltages of the second stage in this example are typically the same as those of the first stage. A second set of 3-bits is thus generated, as well as a second residue voltage, which is coupled to a third stage. The final stage of the PADC flash converts the residue voltage from the next-to-last stage to a desired number of bits, often the same number as the preceding stages. No MDAC is needed in the final stage since no residue voltage needs to be generated. In this manner, if each of three stages in this example PADC have 3-bit resolution, an input signal is converted to 9-bit resolution using a total of twenty-four comparators, rather than the 2^9 comparators (512) that a pure flash ADC would need.
It is well known to those familiar with the art that many PADCs utilize a gain of 2^(n−1) rather than 2^n in the MDAC, providing additional dynamic range to facilitate error correction in succeeding stages. It is also well known that the number of bits resolved by each stage may differ. For example, a PADC may have 4-bit resolution in the first stage, and 3-bit resolution in succeeding stages.
The typical PADC stage has an analog sample/hold (S/H) ahead of the MDAC, and a second sample/hold ahead of the flash ADC. If the sampling times of these MDAC and flash ADC sample/holds differ while the input voltage is changing, an error known as dynamic offset is generated, causing an error in the residue voltage generated in the stage. To decrease this error, an additional input sample/hold circuit is typically placed ahead of the MDAC S/H and flash ADC S/H of the first stage. Because this input S/H typically stores the sampled voltage on a capacitor, the die size of an integrated circuit is increased by the relatively large area required by this capacitor. The input S/H also typically utilizes a buffer amplifier having a high input impedance to buffer the voltage on this capacitor from the following circuitry. The input dynamic range of this buffer amplifier is limited by the peak to peak supply voltage for the amplifier. A PADC operable without this input S/H and its associated buffer amplifier is therefore desirable, as it would reduce die area and allow a wider dynamic range at the input for a given power supply voltage.